A Fast and Accurate FPGA-Based Fault Injection System
In 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (): 236-236, 2013.
Keywords: fault simulation, field programmable gate arrays, hardware description languages, integrated circuit reliability, logic design, network routing, fast FPGA-based fault injection system, accurate FPGA-based fault injection system, RTL, port structure, placed and routed FPGA design, RT/gate-level circuit description, ISCAS’89 benchmark circuits, VHDL netlist, LEON3 system, fault injection tool, recompilation process, Circuit faults, Field programmable gate arrays, Emulation, Logic gates, Hardware, Libraries, Ports (Computers), FPGA synthesis, fault injection, fault emulation, reliability
This paper introduces an FPGA-based fault injection system. To realize this system a library was developed, which implements a static mapping between a circuit described at RTL or gate-level and its corresponding placed and routed FPGA design. The aim of this mapping is to preserve module and port structure of the placed and routed FPGA design to the RT/gate-level circuit description. To demonstrate the accuracy of this mapping the ISCAS’89 benchmark circuits and the VHDL netlist of the LEON3 system are used. The results show that about 99% of the ports in the RT/gate-level circuit description can be located in the placed and routed FPGA design. Based on this library a fault injection tool was developed to accelerate the fault injection experiment time by bypassing some stages (synthesis, placement and routing) of a re-compilation process. In these experiments a 12 × speedup was achieved when compared to fault injections based on serial fault emulation.