Modeling the VTA Machine Learning Accelerator in ACADL for Performance Predictions
Bachelor’s Thesis / Master’s Thesis / Student Research Project
Abstract modeling of HW/SW systems is a relatively new research topic. This technique aims to capture only the essential parameters of software and hardware that influence their timing behavior.
This student project’s goal is to model the VTA Machine Learning Accelerator using the Abstract Computer Architecture Description Language (ACADL) and use different methods for runtime/performance prediction and compare those against the cycle-accurate hardware model.
Block diagram of the VTA Architecture (source)
An Example of a simple machine learning accelerator modelled with ACADL is presented here:
- Successfully atteded the lecture “Grundlagen der Rechnerarchitektur” and/or “Parallele Rechnerarchitekturen” (optional)
- Linux (optional)