Design and implementation of a bit-serial accelerator architecture based on UltraTrail
Master’s Thesis
Abstract
UltraTrail is a low-power hardware accelerator for deep neural networks (DNN) developed at our chair. To reduce memory overhead and computational cost, both DNN parameters and input features are quantized to fixed-point numbers with small bitwidth (e.g. 8 bit). While it is possible to freely change the used datatype during design time, once the chip is manufactured, it will stay fixed. One approach of maintaining flexibility even in the final chip is to use bit-serial computation. Here, the operands are processed bit by bit, instead of a single operation.
The goal of this work is to extend or redesign the current UltraTrail implementation with a bit-serial dataflow and to explore the benefits or drawbacks of such a design.
Requirements
- Successfully atteded the lecture “Entwurf und Synthese Einbetteteter Systeme” or knowledge in hardware design using SystemVerilog or VHDL
- Basic knowledge in deep neural networks (optional)
- Python (optional)