Embedded Systems

Design and Implementation of an Instruction Trace Translator

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Abstract

A popular method of performance evaluation of software-hardware-systems is the analysis of instruction traces generated by instruction set simulators or real hardware components. However, there are many different assembler variants which often are not directly comparable to each other. Goal of this thesis/research project is it to design and implement a modular instruction set translator which takes real instruction traces from different hardware platforms as input and translates them into an abstract instruction trace which only represents selected key features of the trace.

The following example shows a simple for-loop in C and its resulting instruction traces in RISC-V and ARMv7 and a resulting abstract trace for RISC-V and ARMv7.

C Code:

int a = 54;

for(int i = 3; i > 0; i--) {
    a = a + 42;
}

a = a << 1;

RISC-V instruction trace

00000088  addi t2, zero, 0x36   t2=0x00000036
0000008c  addi t0, zero, 0x3    t0=0x00000003
00000090  addi t2, t2, 0x4a     t2:0x00000036, t2=0x00000060
00000094  sub  t0, t0, 0x1      t0:0x00000003, t0=0x00000002
00000098  bne  t0, zero, -8     t0:0x00000002
00000090  addi t2, t2, 0x4a     t2:0x00000060, t2=0x0000008a
00000094  sub  t0, t0, 0x1      t0:0x00000002, t0=0x00000001
00000098  bne  t0, zero, -8     t0:0x00000001
00000090  addi t2, t2, 0x4a     t2:0x0000008a, t2=0x000000b4
00000094  sub  t0, t0, 0x1      t0:0x00000001, t0=0x00000000
00000098  bne  t0, zero, -8     t0:0x00000000
0000009c  srli t2, t2, 0x1      t2:0x000000b4, t2=0x0000005a
000000a0  sw   t2, zero, 0x1004 t2:0x0000005a, MEM:0x00001004

ARMv7 instruction trace

0000005c  mov  r5, 0x36         r5=0x00000036
00000060  mov  r1, 0x3          r1=0x00000003
00000064  add  r5, r5, 0x4a     r5:0x00000036, r5=0x00000060
00000068  sub  r1, r1, 0x1      r1:0x00000003, r1=0x00000002
0000006c  cmp  r1, 0x0          r1:0x00000002, z=0x0
00000070  bne  -12              z:0x0
00000064  add  r5, r5, 0x4a     r5:0x00000060, r5=0x0000008a
00000068  sub  r1, r1, 0x1      r1:0x00000003, r1=0x00000002
0000006c  cmp  r1, 0x0          r1:0x00000002, z=0x0
00000070  bne  -12              z:0x0
00000064  add  r5, r5, 0x4a     r5:0x0000008a, r5=0x000000b4
00000068  sub  r1, r1, 0x1      r1:0x00000003, r1=0x00000002
0000006c  cmp  r1, 0x0          r1:0x00000002, z=0x0
00000070  bne  -12              z:0x0
0000007a  lsr  r5, r5, 0x1      r5:0x000000b4, r5=0x0000005a
00000078  mov  r4, 0x2056       r4=0x00002056
0000007c  str  r5, [r4]         r5:0x0000005a, MEM:0x00002056

resulting abstract instruction trace from RISC-V

00000022  52  alu     []    
00000023  53  alu     []    
00000024  54  alu     [52]
00000028  55  alu     [53] 
0000002c  56  branch  [55]
00000024  57  alu     [54] 
00000028  58  alu     [56] 
0000002c  59  branch  [58]
00000024  60  alu     [57] 
00000028  61  alu     [59] 
0000002c  62  branch  [61]
00000030  63  alu     [60] 
00000034  64  lsu     [63] 0x00000145

resulting abstract instruction trace from ARMv7

00000025  61 alu    [] 
00000026  62 alu    [] 
00000027  63 alu    [61]
00000028  64 alu    [62]
00000029  65 alu    [64]
00000030  66 branch [65]
00000027  67 alu    [63]
00000028  68 alu    [65]
00000029  69 alu    [68]
00000030  70 branch [69]
00000027  71 alu    [67]
00000028  72 alu    [69]
00000029  73 alu    [72]
00000030  74 alu    [73]
00000031  75 alu    [71]
00000032  76 alu    []
00000033  77 lsu    [75,76] 0x00000145

Requirements

  • Python
  • Assembler
  • Linux (optional)

Contact

Lübeck, Konstantin

Bringmann, Oliver