Embedded Systems

Fully-automated Synthesis of Power Management Controllers from UPF

by Dustin Peterson and Oliver Bringmann
In Proceedings of the 24th Asia and South Pacific Design Automation Conference, pages 76–81. ACM, 2019.

Abstract

We present a methodology for automatic synthesis of power management controllers for System-on-Chip designs by using an extended version of the Unified Power Format (UPF). Our methodology takes an SoC design and a UPF-based power design, and automatically generates a power management controller in Verilog/VHDL that implements the power state machine specified in UPF. It performs a priority-based scheduling for all power state machine actions, connects each power management signal to the corresponding logic wire in the UPF design and integrates the controller into the System-on-Chip using a configurable bus interface. We implemented the proposed approach as a plugin for Synopsys Design Compiler to close the gap in today’s power management flows and evaluated it by a RISC-V System-on-Chip.