Power-Gating Models for Rapid Design Exploration
In 17th IEEE International New Circuits and Systems Conference (In Press), 2019.
Abstract—Power gating (PG) is an effective method to reduce leakage currents in an SoC design during run-time. It dynamically shuts down components using a network of sleep transistors, but requires a detailed analysis to scale this network appropriately with respect to area, wake-up time, in-rush currents, voltage drops and transition energies. In this paper, we present a method to efficiently determine these key parameters for any SoC design and sleep transistor network at gate-level to enable the rapid exploration of power design alternatives while providing sufficient accuracy for high-level design exploration. Compared to SPICE our approach achieves a speed-up of up to 11457x for two ISCAS circuits, a 32-bit multiplier and a RISC-V core, each build for a 90nm PDK. The average error compared to SPICE is 2.6% for peak current and 10% for wake-up energy and delay.