Detecting non-functional circuit activity in SoC designs
In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (): 464-469, 2018.
In this paper, we present a methodology for the automatic detection of non-functional circuit activity in SoC designs. Our methodology formally analyses an RTL design, generates an internal graph representation and traverses the graph using given simulation traces. We evaluate an open source processor with a given set of benchmark applications using our approach. With a commercial RTL simulator, we observe an average register toggle activity of 6.7%-11.5%, but our experiments show that 86.1-92.7% of these toggles are non-functional, i.e. not necessary for producing the exact same circuit output. We further evaluate the efficiency of the clock gating architecture of a commercial ASIP. For the Dhrystone benchmark we show that, even though only 34.7% of the registers are clocked on average, still 64.3% of the non-clock-gated registers in this ASIP are not needed on average to produce exactly the same circuit output.