Development of a Low Power Platform Generation Framework
Assigned to J. Fischer.
The recent growth of the embedded system market emphasised an often undervalued aspect of embedded system design: The development of systems with low power consumption. Transistor shrinking, and thus reduction of dynamic dissipation, these are power dissipation caused by the transistor transitions, used to be a good strategy. With smaller designs other effects started to dominate the power dissipation, namely static dissipation. Such effects are a sole consequence of the physics of small lengths and can therefore neither be efficiently solved by further down-sizing nor by other structure shapes.
A way out of this impasse is given by so called power aware design techniques. Cutting all dissipations to zeros, the most effective is Power Gating, which powers idle regions on the chip down. Since therefore necessary control modules, namely ‘Power Management Controller’ (PMC) cause an increased area usage, the realisation of gated regions is a trade-off. Furthermore the practical implementation is still cumbersome. To find the best parametrization of power gated designs, it is necessary to enable the fast generation differently parametrized power aware designs for further testing and the later final design.
To this end the thesis introduces a general framework, capable of introducing power aware approaches in given reference designs. Thereby the logic is modelled in Verilog and the power behaviour file is outputted in the ‘Unified Power Format’ (UPF). As a proof of concept, the implementation of Power Gating is discussed and tested for two different PMC layouts, namely the Single PMC, and a Master Slave approach. Moreover this work shows, via simulation of the power gated designs, that the framework generates reasonable results. It also points out, that certain programs in the tool chain have critical issues with the handling of UPF, which limits the range of validity of this framework.