Embedded Systems

Spatial and temporal granularity limits of body biasing in UTBB-FDSOI

by Johannes M. Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, and Wolfgang Rosenstiel
In 2015 Design, Automation Test in Europe Conference Exhibition (DATE) (): 876-879, 2015.

Keywords: circuit analysis computing, reconfigurable architectures, silicon-on-insulator, temporal granularity, UTBB-FDSOI, SOI technology, performance characteristics, electrical task, substrate potential, dynamic voltage scaling, finer island sizes, body bias islands, body bias combinations, energy efficiency, timing constraints, combination based analysis tool, optimized body bias island partitions, body biasing levels, optimized body bias assignments, dynamic body biasing, dynamically switching body biases, power consumption, additional circuitry, switching overheads, application specific switching strategies, frequency scaling scenario, forward body biasing, dynamic reconfigurable processor, DRP design, Switches, Layout, Clocks, Optimization, Delays, Power demand


Advances in SOI technology such as STMicro’s 28nm UTBB-FDSOI enabled a renaissance of body biasing. Body biasing is a fast and efficient technique to change power and performance characteristics. As the electrical task to change the substrate potential is small compared to Dynamic Voltage Scaling, much finer island sizes are conceivable. This however creates new challenges in regard to design partitioning into body bias islands and body bias combinations across such designs. These combinations should be chosen so that energy efficiency improves while maintaining timing constraints. We introduce a combination based analysis tool to find optimized body bias island partitions and body biasing levels. For such partitions, optimized body bias assignments for static, programmable and dynamic body biasing can be computed. The overheads incurred by dynamically switching body biases are estimated to yield actual improvements and to give an upper bound for the power consumption of required additional circuitry. Based on these partitionings and the switching overheads, optimized application specific switching strategies are computed. The effectiveness of this method is demonstrated in a frequency scaling scenario using forward body biasing on a Dynamic Reconfigurable Processor (DRP) design. We show that leakage can be greatly reduced using the proposed methods and that dynamic body biasing can be beneficial even at small time periods.