Embedded Systems

Advancing Source-Level Timing Simulation using Loop Acceleration

by Joscha Benz, Christoph Gerum, and Oliver Bringmann
In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1393–1398. IEEE, 2018.


Source-level timing simulation (STLS) is an important technique for early examination of timing behavior, as it is very fast and accurate. A factor occasionally more important than precision is simulation speed, especially in design space exploration or very early phases of development. Additionally, practices like rapid prototyping also benefit from highperformance timing simulation. Therefore, we propose to further reduce simulation run-time by utilizing a method called loop acceleration. Accelerating a loop in the context of SLTS means deriving the timing of a loop prior to simulation to increase simulation speed of that loop. We integrated this technique in our SLTS framework and conducted an comprehensive evaluation using the Ma¨lardalen benchmark suite. We were able to reduce simulation time by up to 43% of the original time, while the introduced accuracy loss did not exceed 8 percentage points.