Optimzation of a hardware accelerater for fast Fourier Transformation (FFT)
Fast Fourier Transformation (FFT) is a crucial algorithm for many signal processing applications and we use it as feature extractor for our neural networks. We have generated a hardware accelerator for FFT computations using a high level synthesis. It turns out that this module is quite power hungry. Your task would be to find an optimized version of the accelerator using a high level synthesis tool or by implementing some existing approaches. For the evaluation the Globalfoundries 22 nm process is used.
- Sucessfully passed ESES lecture or knowledge of hardware design using Verilog or VHDL