Embedded Systems

Design of a hardware accelerater for MFCC

Master’s Thesis

Abstract

Mel-frequency cepstral coefficients (MFCCs) are widely used as input features in speech recognition systems. The main steps to derive MFCC features are a Fourier transformation, mapping to the mel scale and a discrete cosine transformation. We use MFCC features as inputs for neural networks which are accelerated in hardware to obtain an energy efficient realtime execution. To complete the hardware accelerated pipeline a hardware implementation (HDL) of MFCC features is needed.

Requirements

  • Sucessfully passed ESES lecture or knowledge of hardware design using Verilog or VHDL

Contact

Bringmann, Oliver

Frischknecht, Adrian

Lübeck, Konstantin